`include "code\source\P2\channel.v"
`timescale 1ns/1ps

module tb_channel;

// Input
reg clk, clk2;
reg rst_n;
reg din, din_valid;

// Output
wire dout, dout_valid;

channel u_channel(
            .clk (clk ),
            .clk2 (clk2 ),
            .rst_n (rst_n ),
            .din (din ),
            .din_valid (din_valid ),
            .dout (dout ),
            .dout_valid (dout_valid )
        );

initial begin
    $dumpfile("./release/test_channel.vcd");
    $dumpvars(0, tb_channel);
end

always begin
    #2.5
     clk2 = ~clk2;
    #2.5
     clk2 = ~clk2;
    clk = ~clk;
end

initial begin
    clk <= 0;
    clk2 <= 1;
    rst_n <= 0;
    din <= 0;
    din_valid <= 0;
    #10;
    rst_n <= 1;
    #10
    din_valid <= 1;

    din <= 1;
    #80
     din <= 0;
    #80;
    din <= 1;
    #80
     din <= 0;
    #80;
    din_valid <= 0;
    #1000
     $finish;
end


endmodule
